Field of Invention
The present invention relates to a dual constant time buck-boost switching regulator. Particularly, it relates to a current mode or voltage mode buck-boost switching regulator with two sets of constant time. The present invention also relates to a control circuit and a control method of the dual constant time buck-boost switching regulator.
Description of Related Art
FIG. 1A shows a prior art method of controlling a buck-boost switching regulator disclosed in U.S. Pat. No. 6,166,527. The constant time buck-boost switching regulator comprises an inductor L, four power switches A, B, C, and D, and a control circuit 20. The control circuit 20 controls the operation of the power switches A, B, C and D to convert an input voltage Vin to an output voltage Vout, wherein the input voltage Vin may be higher or lower than the output voltage Vout, and hence the regulator may need to operate in buck conversion (i.e. step down) or boost conversion (i.e. step up). In the control circuit 20, an error amplifier 22 compares a feedback signal FB (which relates to the output voltage Vout) with a reference voltage Vref to generate an error amplified signal Vea. PWM (Pulse Width Modulation) comparators 24 and 25 compare the error amplified signal Vea with voltage wave signals VX and VY respectively. A logic circuit 29 generates switch control signals VA, VB, VC, and VD to control the power switches A, B, C, and D respectively according to the comparing results from the comparator 24 and 25.
FIG. 1B shows waveforms of the error amplified signal Vea, the voltage wave signals VX and VY, and the switch control signals VA, VB, VC and VD. When the error amplified signal Vea is between level V1 and level V2, the regulator operates in a pure buck conversion mode. When the error amplified signal Vea is between level V2 and level V3, the regulator operates in a buck-boost conversion mode. When the error amplified signal Vea is between level V3 and level V4, the regulator operates in a pure boost conversion mode. When the regulator is operating in the pure buck conversion mode, the power switch C is kept OFF and the power switch D is kept ON. When the regulator is operating in the pure boost conversion mode, the power switch A is kept ON and the power switch B is kept OFF. When the regulator is operating in the buck-boost conversion mode, as shown in the FIG. 1B, the switch control signals VA and VB are generated according to the relationship between the error amplified signal Vea and the voltage wave signal VX, and the switch control signals VC and VD are generated according to the relationship between the error amplified signal Vea and the voltage wave signal VY; in other words, the regulator performs a mixed combination of boost conversion (the power switches C and D operating) and buck conversion (the power switches A and B operating).
The aforementioned prior art buck-boost regulator includes the pure boost conversion mode, the pure buck conversion mode and the buck-boost conversion mode, wherein the buck-boost conversion mode requires an operation range, that is, level V2 must be lower than level V3; otherwise, the prior art system will be unstable. When operating in the buck-boost conversion mode, all four switches A, B, C and D are switching in one cycle period, and this will increase the switching loss as well as the power consumption. The prior art has a drawback that there is a conflict between meeting the stability requirement and keeping the power loss low.
FIG. 2A shows the circuit structure of another prior art U.S. Pat. No. 7,176,667. This prior art uses the error amplifier 22 to generate two error amplified signals Vea1 and Vea2, one of which is selected to be compared with a voltage wave signal OSC by the PWM comparators 24. The circuit further includes a constant pulse width generator 26. Based on the outputs from the PWM comparator 24 and the constant pulse width generator 26, the logic circuit 29 generates the switch control signals VA, VB, VC, and VD to control the power switches A, B, C, and D respectively.
Referring to FIG. 2B, there are four conversion modes in U.S. Pat. No. 7,176,667: besides the pure buck conversion mode M1 and the pure boost conversion mode M4, a transient buck conversion mode M2 and a transient boost conversion mode M3 are provided between M1 and M4. The switch control signals VA and VB follow the output of the PWM comparators 24 and the switch control signals VC and VD have constant pulse widths in the transient buck conversion mode M2. The switch control signals VC and VD follow the output of the PWM comparators 24 and the switch control signals VA and VB have constant pulse widths in the transient boost conversion mode M3.
The aforementioned prior art U.S. Pat. No. 7,176,667 has the following drawbacks: four conversion modes require more complicated control mechanism; with the two transition modes (M2 and M3), it means that there is more chance for the circuit to operate in the transient modes in which all the four power switches will be switching and will increase the switching loss and the power consumption.
Besides, both the prior art regulators shown in U.S. Pat. Nos. 6,166,527 and 7,176,667 are based on fixed frequency operation. The transient response of this kind of technology is usually slower due to fixed switching frequency which limits the bandwidth. To realize the aforementioned prior art regulators in PFM mode (Pulse Frequency Modulation), extra complicated circuits are required to cope with conditions such as a very low load current, and in some cases it even cannot operate in PFM mode when for example the input voltage Vin is close to the output voltage Vout. FIG. 3 shows a prior art TPS63020 controller which similarly operates with fixed frequency and includes a buck-boost overlap control which is similar to the aforementioned buck-boost mode or transient modes. This prior art of FIG. 3 uses an average current mode which needs a slope compensation circuit to suppress the tendency of sub-harmonic oscillation, and thus the circuitry becomes even more complicated.
FIG. 4A shows the structure of another prior art US 2011/0156685A1. The buck-boost regulator includes an inductor L, power switches A, B, C, and D, and a control circuit 30. The control circuit 30 controls the switching of the power switches A, B, C, and D to convert the input voltage Vin to the output voltage Vout. The error amplifier 32 of the control circuit 30 compares a feedback signal FB (which relates to the output voltage Vout) with a reference voltage Vref to generate an error amplified signal. The PWM comparator 34 compares the error amplified signal with an inductor current related signal. The ON time generation circuit 37 generates an ON time for the switches according to the comparing result of the PWM comparator 34. The driver circuit 39 generates switch control signals VA, VB, VC, and VD to control the power switches A, B, C, and D according to the ON time. This prior art has a feature that only one PWM comparator 34 is needed because only one ON time is required. Though the structure of this prior art is simple for implementing a buck-boost PWM regulator, this prior art has a drawback that all of the power switches A, B, C, and D are switching in each operating cycle. As shown in FIGS. 4B and 4C, the power switches A and C are turned ON first (the current direction is as shown by the solid line in FIG. 4C), and then the power switches B and D are turned ON (the current direction is as shown by the dashed line in FIG. 4C), and such operations repeat. Hence, the switching loss is much higher.
To overcome the drawbacks of the aforementioned prior art circuits, the present invention provides a constant time buck-boost switching regulator which has fast transient response, which does not need slope compensation, which can cooperate in PFM without extra complicated circuits, and which furthermore can operate in pure buck conversion mode and pure boost conversion mode without a buck-boost conversion mode or a transient buck mode or a transient boost mode.